Semiconductor device, method of manufacture thereof, circuit board, and electronic device

ABSTRACT

A semiconductor device has first and second substrates ( 10, 20 ) disposed so as to be overlaid, and a semiconductor chip ( 30 ) mounted on each of the first and second substrates ( 10, 20 ). A first interconnect pattern ( 12 ) formed on the first substrate ( 10 ) has bent portions ( 16 ) which project from the surface of the first substrate ( 10 ). The bent portions ( 16 ) are bonded to a flat portion ( 26 ) of a second interconnect pattern ( 22 ) formed on the second substrate ( 20 ).

TECHNICAL FIELD

The present invention relates to a semiconductor device and method ofmanufacturing the same, a circuit board, and an electronic instrument.

BACKGROUND ART

Conventionally, it is known for a semiconductor device to have asubstrate on which an interconnect pattern is formed (an interposer),and to have a semiconductor chip mounted on the interposer. Withincreasing miniaturization of semiconductor devices and increasing pincounts, the interconnect pattern is required to be even finer, but thereare limits to the degree to which the interconnect pattern formed on asingle interposer can be made finer. In addition, multi-layer substratesare expensive.

In this case, by using a plurality of interposers, increasing pin countscan be supported. For example, a stack type of semiconductor device hasbeen developed, having a construction in which a plurality ofinterposers is adhered together, with semiconductor chips mounted on oneside or both sides.

As a published example may be cited Japanese Patent Publication No.2870530, in which by means of bumps, interconnect patterns formed on theupper and lower interposers are electrically connected together.However, with this method, the formation of the bumps involves time andcost, and this is a problem.

The present invention solves the above described problem, and has as itsobject the provision of a semiconductor device and method of manufacturethereof, a circuit board and an electronic instrument in which thesubstrates are electrically connected with a simple construction.

DISCLOSURE OF THE INVENTION

(1) A semiconductor device of the present invention comprises:

a plurality of substrates which have interconnect patterns and aredisposed so as to be overlaid; and

a semiconductor chip mounted on at least one of the substrates;

wherein a first interconnect pattern formed on a first substrate whichis one of two substrates included in the plurality of overlaidsubstrates has at least one bent portion which projects from a surfaceof the first substrate; and

wherein the bent portion is electrically connected to at least one flatportion of a second interconnect pattern formed on a second substrate ofthe two substrates.

The bent portion is formed by a portion of the first interconnectpattern projecting from the surface of the first substrate, and has asimple construction. Since the electrical connection between the twosubstrates is achieved by means of the bent portion, the formation ofbumps is not required.

(2) In this semiconductor device, a through hole may be formed in thefirst substrate, and the bent portion may enter the through hole andproject from a surface of the first substrate opposite to the surface onwhich the first interconnect pattern is formed.

By means of this, the first interconnect pattern is formed on thesurface of the first substrate opposite to that from which the bentportion projects. Therefore, since the first substrate is interposedbetween the first and second interconnect patterns, short-circuitsbetween the two can be prevented.

(3) In this semiconductor device,

a through hole may be formed in the first substrate; and

the bent portion may be positioned over the through hole and projectfrom the surface of the first substrate on which the first interconnectpattern is formed.

By means of this, since the bent portion projects from the surface ofthe first substrate on which the first interconnect pattern is formed,the bent portion can be formed to be higher than the surface of thefirst substrate.

(4) In this semiconductor device, a plurality of the bent portions maybe formed within or over the through hole.

By means of this, it is sufficient to form one through holecorresponding to a plurality of bent portions.

(5) In this semiconductor device,

a plurality of the through holes may be formed in the first substrate;

a plurality of the bent portions may be formed in the first interconnectpattern; and

each of the bent portions may be formed so as to be positioned over oneof the through holes.

By means of this, since the material of the first substrate is presentbetween adjacent bent portions, short-circuits between the bent portionscan be prevented.

(6) In this semiconductor device, the second interconnect pattern may beformed on a surface of the second substrate on the side of the firstsubstrate.

By means of this, since the second interconnect pattern is close to thefirst substrate, even if the bent portions are low, the electricalconnection to the flat portion is possible.

(7) In this semiconductor device,

the second interconnect pattern may be formed on a surface of the secondsubstrate opposite to the surface of the second substrate which faces tothe first substrate; and

the bent portion may be electrically connected to the secondinterconnect pattern through the through hole formed in the secondsubstrate.

By means of this, because the second substrate is interposed between thefirst and second interconnect patterns, short-circuits between the twoare prevented.

(8) In this semiconductor device,

the semiconductor chip may be provided between the first and secondsubstrates; and

the bent portion may project to the side of the semiconductor chip, andbe formed to be higher than the semiconductor chip.

By means of this, without impeding the presence of the semiconductorchip, the electrical conduction between the first and second substratescan be assured. By means of the bent portions, a space greater than theheight of the semiconductor chip can be provided between the first andsecond substrates, and separate provision of a spacer for maintainingthe spacing is not required.

(9) In this semiconductor device, the semiconductor chip may be providedon each of the first and second substrates.

This is a stack type of semiconductor device having a plurality ofoverlaid semiconductor chips.

(10) In this semiconductor device, the semiconductor chip may beprovided on one of the first and second substrates.

By means of the first and second interconnect patterns, a multi-layerinterconnect can be formed.

(11) In this semiconductor device,

the number of the substrates provided to be overlaid may be three ormore;

a central substrate of the three substrates may be the first substrate,and the bent portions may project from both surfaces of the firstsubstrate; and

outer substrates of the three substrates maybe the second substrate.

By means of this, the bent portions of the interconnect pattern formedon the central substrate are electrically connected to the flat portionof the interconnect patterns formed on the outer substrates.

(12) In this semiconductor device,

the number of the substrates provided to be overlaid may be three ormore; and

a central substrate of the three substrates may be the second substrate,and outer substrates may be the first substrate.

By means of this, the flat portion of the interconnect pattern formed onthe central substrate is electrically connected to the bent portions ofthe interconnect patterns formed on the outer substrates.

(13) In this semiconductor device,

the number of the substrates provided to be overlaid may be three ormore;

one of two outer substrates of the overlaid substrates may be the firstsubstrate, and the other may be the second substrate; and

at least one center substrate of the overlaid substrates may have thebent portion and the flat portion, and may be the first substrate withrespect to one of the two outer substrates, and may be the secondsubstrate with respect to the other of the two outer substrates.

By means of this, the center substrate is constituted to function asboth the first and second substrates.

(14) A circuit board of the present invention has the above describedsemiconductor device mounted.

(15) An electronic instrument of the present invention has the abovedescribed semiconductor device.

(16) A method of manufacture of a semiconductor device of the presentinvention comprises the steps of:

mounting a semiconductor chip on at least one of a plurality ofsubstrates having interconnect patterns;

providing the substrates so as to be overlaid; and

electrically connecting two substrates of the overlaid substrates;

wherein a first interconnect pattern formed on a first substrate of thetwo substrates has a bent portion which projects from a surface of thefirst substrate; and

wherein the bent portion is electrically connected to a flat portion ofa second interconnect pattern formed on a second substrate of the twosubstrates.

According to the present invention, the bent portion is formed by aportion of the first interconnect pattern projecting from the surface ofthe first substrate, and have a simple construction. Since theelectrical connection between the two substrates is achieved by means ofthe bent portion, the formation of bumps is not required.

(17) In this method of manufacture of a semiconductor device, theplurality of substrates may be positioned with the outer form of thesubstrates as a reference.

(18) In this method of manufacture of a semiconductor device, theplurality of substrates maybe positioned with holes formed in thesubstrates as a reference.

(19) In this method of manufacture of a semiconductor device, at leastone of pressure and heat may be applied to the bent portion toelectrically connect the bent portion to the flat portion.

(20) In this method of manufacture of a semiconductor device,

the bent portion may be formed on each of the interconnect patternsformed on the substrates; and

the bent portion formed on each of the substrates may be electricallyconnected to the flat portion in a single operation.

By means of this, the electrical connection of the plurality of bentportions and the plurality of flat portions can be carried out in asingle operation, and the process can be made shorter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first embodiment of the semiconductor device to which thepresent invention is applied;

FIG. 2 shows a first substrate of the first embodiment of thesemiconductor device to which the present invention is applied;

FIG. 3 shows a modification of the first embodiment;

FIG. 4 shows a modification of the first embodiment;

FIG. 5 shows the method of manufacture of the first embodiment of thesemiconductor device to which the present invention is applied;

FIG. 6 shows the method of manufacture of the first embodiment of thesemiconductor device to which the present invention is applied;

FIG. 7 shows the method of manufacture of the semiconductor device towhich the modification of the first embodiment applies;

FIG. 8 shows a second embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 9 shows a third embodiment of the semiconductor device to which thepresent invention is applied;

FIG. 10 shows a fourth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 11 shows a fifth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 12 shows a sixth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 13 shows a seventh embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 14 shows an eighth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 15 shows a ninth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 16 shows a tenth embodiment of the semiconductor device to whichthe present invention is applied;

FIG. 17 shows an embodiment of a circuit board to which the presentinvention is applied;

FIG. 18 shows an embodiment of an electronic instrument to which thepresent invention is applied; and

FIG. 19 shows an embodiment of an electronic instrument to which thepresent invention is applied.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention is now described in terms of preferredembodiments, with reference to the drawings.

First Embodiment

FIG. 1 shows a first embodiment of the semiconductor device to which thepresent invention is applied. The semiconductor device comprises firstand second substrates 10 and 20. It should be noted that in asemiconductor device having three or more substrates, any particular twoof these substrates are the first and second substrates 10 and 20. Thefirst and second substrates 10 and 20 may be two immediately adjacentsubstrates.

On each of the first and second substrates 10 and 20 an interconnectpattern (in this embodiment, first and second interconnect patterns 12and 22) are formed. With the first and second interconnect patterns 12and 22 formed, the first and second substrates 10 and 20 can be referredto as interconnect substrates.

The material of the first and second substrates 10 and 20 may be eitheran organic material or an inorganic material. As organic materials maybe used polyimide, polyester, polysulfone resins, or the like, and as aninorganic material may be used silicon, glass, ceramic, metal, or thelike, and a combination of organic and inorganic materials may also beused.

As examples of the first and second substrates 10 and 20 may cited aflexible substrate formed of a polyimide resin (such as for example aTAB tape (Tape Automated Bonding Tape), a ceramic substrate, a glasssubstrate, and a glass epoxy substrate.

In this embodiment, in the first and second substrates 10 and 20 isformed at least one (one, or a plurality of) through holes (or vias oropening) 14 and 24. FIG. 2 is a plan view of the first substrate 10. Thethrough holes 14 are formed to avoid the mounting region of asemiconductor chip 30. A through hole 14 maybe, as shown in FIG. 2, aslot coinciding with a plurality of bent portions 16, or may be of asize such as to coincide with only one bent portion 16.

The through holes 24 formed in the second substrate 20 are also formedto avoid the mounting region of the semiconductor chip 30. One throughhole 24 maybe slot into which enter the ends of a plurality of bentportions 16, or may be of a size such that the end of only one bentportion 16 enters.

The first and second interconnect patterns 12 and 22 may be formed onsingle sides of the first and second substrates 10 and 20, or may beformed on both sides. The first and second interconnect patterns 12 and22 may have formed lands for connection to electrodes (pads) of thesemiconductor chip 30 or external terminals 40. Except for theelectrically connected portions (for example, lands, bent portions 16,flat portion 26), the first and second interconnect patterns 12 and 22are preferably covered with a protective layer of solder resist or thelike.

The first and second interconnect patterns 12 and 22 may be adhered byan adhesive (not shown in the drawings) to the first and secondsubstrates 10 and 20, constituting a three-layer substrate. In thiscase, the first and second interconnect patterns 12 and 22 are commonlyformed by etching a metal foil of copper foil or the like or aconducting foil. The metal foil of copper foil or the like or conductingfoil is first adhered to the first and second substrates 10 and 20 by anadhesive (not shown in the drawings).

The first and second interconnect patterns 12 and 22 may be constructedof multiple layers. For example, after laminating a film of any ofcopper, chromium, titanium, nickel, or titanium-tungsten, this may beetched to form first and second interconnect patterns 12 and 22. For theetching, photolithography may be applied.

Alternatively, the first and second interconnect patterns 12 and 22 maybe formed on the first or second substrate 10 without an adhesive, toconstitute a two-layer substrate. In a two-layer substrate, a thin filmis formed by sputtering or the like, and plating is carried out, to formthe first and second interconnect patterns 12 and 22. The first andsecond interconnect patterns 12 and 22 may also be formed by theadditive method. Even if a two-layer substrate, the first and secondinterconnect patterns 12 and 22 have a thickness sufficient to allowplastic processing.

As the first and second substrates 10 and 20 (interconnect substrates)on which the first and second interconnect patterns 12 and 22 are formedmay equally be employed a built-up interconnect board constructed froman insulating resin and interconnect pattern which are laminated, or amulti-layer substrate in which a plurality of substrates are laminated,or a double-sided substrate or the like.

On the interconnect pattern 12 is formed at least one (one or aplurality of) bent portions 16. Linear portions (interconnects) of theinterconnect pattern 12 are bent, forming the bent portions 16. The bentportions 16 project from the surface of the first substrate 10. The endsof the bent portions 16 are, as shown in FIG. 1, bent in a rounded form.The bent portions 16 are formed by plastic deformation of a part of thefirst interconnect pattern 12. If the first interconnect pattern 12 isflexible, the bent portions 16 will also be flexible.

As a modification, bent portions 56 shown in FIG. 3 have substantiallylevel apices. With the bent portions 56, by means of the level apices,the area of contact with another interconnect pattern (in practice thesecond interconnect pattern 22) is increased, and a more positiveelectrical conduction can be ensured. The description of this embodimentcan also be applied to this modification.

On the projected surface of the bent portions 16 shown in FIG. 1, thatis, the surface contacting the second interconnect pattern 22, platingis preferably carried out to better ensure positive electricalconduction. For example, tin or solder plating may be applied, anoxidation resistant gold plating may be applied.

The bent portions 16 are formed to coincide with the through holes 14. Aplurality of bent portions 16 is formed so as to coincide with a singlethrough hole 14. In this embodiment, the bent portions 16 do not enterthe through holes 14. In more detail, the bent portions 16 are formedover the through holes 14 to project from the surface of the firstsubstrate 10 on which the first interconnect pattern 12 is formed.

As a modification, bent portions 66 shown in FIG. 4 enter through holes64 formed in a first substrate 60. In more detail, the bent portions 66project from the surface of the first substrate 60 opposite to thesurface on which a first interconnect pattern 62 is formed. Theformation is such that one bent portion 66 and one through hole 64coincide. The bent portions 66 have a domed form. The bent portions 66are formed by plastic deformation of the portions blocking the throughholes 64 in the first interconnect pattern 62 (the portions larger thanthe through holes 64). In the process of formation, provided it iswithin the limits of not interfering with electrical conduction, breaks(cracks) of the bent portions 66 may occur. The description of thisembodiment can also be applied to this modification.

It should be noted that if an adhesive is interposed between the firstsubstrate 60 and the first interconnect pattern 62, when the bentportions 66 are formed, adhesive may be present between the throughholes 64 and the bent portions 66. By virtue of this, thermal stressapplied to the bent portions 66 can be absorbed by the adhesive.

As shown in FIG. 1, when the semiconductor chip 30 is disposed on theside from which the bent portions 16 project, the bent portions 16 areformed to be higher than the semiconductor chip. In more detail, thebent portions 16 have their extremities formed to extend past thesurface of the semiconductor chip 30 opposite the first substrate 10,and contact the second interconnect pattern 22.

The second interconnect pattern 22 has at least one (one or a pluralityof) flat portion 26. In other words, other than in the flat portion 26,the second interconnect pattern 22 may have bent portions (with the samenature as the bent portions 16) formed. The flat portion 26 is formed tocoincide with the through holes 24. As a result, with the through holes24 interposed, electrical connection with the flat portion 26 ispossible.

Here the flat portion 26 may have a level surface such as to contact theend surface of the bent portions 16, but not to contact the sidesurface. Therefore, the flat portion 26 may be bent in the directionfacing the bent portions 16. Alternatively, the flat portion 26 may be abump (projection) formed on the second interconnect pattern 22 byplating or half-etching or the like. If the flat portion 26 projects inthe direction of the bent portions 16, the amount of bending of the bentportions 16 is reduced, and the generation of cracks at the time offormation can be prevented. In this case, the portion of electricalconnection of the first and second interconnect patterns 12 and 22includes the bumps (flat portion 26), but also includes the bentportions 16. Therefore, even in this example, there is a distinctionfrom the prior art in which the electrical connection is by means of thebumps only.

The first and second substrates 10 and 20 are disposed so as to beoverlaid. It is sufficient for the first and second substrates 10 and 20to overlap at least partially. If first and second substrates 10 and 20are of the same size and shape, they may overlap completely.

In this embodiment, the second interconnect pattern 22 is positioned onthe opposite side of the second substrate 20 from the first substrate10. Through the through holes 24, the bent portions 16 formed on thefirst interconnect pattern 12 are electrically connected to the flatportion 26 of the second interconnect pattern 22.

For the electrical connection, it is sufficient for the metal (forexample, formed by plating) formed on the surfaces of the bent portions16 and flat portion 26 to be bonded. More specifically, metal bonds maybe gold-gold, gold-tin, solder, or the like. For the metal bond,single-point bonding may be applied, and ultrasound, heat or pressuremay be applied to diffuse the materials. Furthermore, a mechanicalpressure welding by means of crimping or the like may be applied.

By means of brazing such as soldering, or using a conducting paste(resin including silver paste or the like) or conducting adhesive, orthe like, the bent portions 16 and the flat portion 26 may beelectrically connected.

For the electrical connection between the bent portions 16 and the flatportion 26, an anisotropic conducting adhesive material may be used. Theanisotropic conducting adhesive material is an adhesive material whichconducts only in the direction in which pressure is applied, and has asthe adhesive a resin in which are dispersed particles of a metal such asaluminum or particles of resin to which a metal coating has beenapplied. This may be an anisotropic conducting film (ACF) which isformed in a sheet form and is used by adhering to the points ofadhesion, or an anisotropic conducting adhesive (ACP) which is formed inpaste form, and is used by being spread on the points of adhesion.

Alternatively, an adhesive in which conducting particles are not mixedmay be used. For example, using the contraction force of an insulatingresin, the bent portions 16 and flat portion 26 may be bonded. In thiscase, an adhesive in which conducting particles are not mixed will beless expensive, and therefore the semiconductor device manufacture canbe achieved at lower cost.

The material used for the electrical connection between the bentportions 16 and the flat portion 26 may be the same as that used for theelectrical connection between the semiconductor chip and theinterconnect pattern.

According to this embodiment, the first and second interconnect patterns12 and 22 can be electrically connected. If the bent portions 16 areeasily flexed, the bent portions 16 absorb stress, and the occurrence ofbreaks in the electrical connection portion can be reduced.

In this embodiment, a semiconductor chip 30 is mounted on each of thefirst and second substrates 10 and 20. On the first substrate 10, thefirst interconnect pattern 12 is formed on the side of the secondsubstrate 20, and on this surface the semiconductor chip 30 is mounted.That is to say, the semiconductor chip 30 is disposed between the firstand second substrates 10 and 20. On the second substrate 20, the secondinterconnect pattern 22 is formed on the surface opposite to the firstsubstrate 10, and on this surface the semiconductor chip 30 is mounted.

Alternatively, the semiconductor chip 30 may be mounted on the surfacesof the first and second substrates 10 and 20 opposite to those on whichthe first and second interconnect patterns 12 and 22 are formed. In thiscase, through the electrical connection portion (through holes or viaholes or the like) between both sides of the first and second substrates10 and 20, the electrical connection between the semiconductor chip 30and the first and second interconnect patterns 12 and 22 is achieved.

It should be noted that the semiconductor device of the presentinvention has a plurality of substrates, and a semiconductor chipmounted on one of the substrates. Therefore, a semiconductor chip may bemounted on one only of the first and second substrates, or asemiconductor chip may be mounted on a substrate other than the firstand second substrates.

In this embodiment, face-down mounting is applied as the mountingmethod. In the face-down mounting method, for the electrical connectionbetween the bumps on the semiconductor chip 30 and the interconnectpatterns (for example, the first and second interconnect patterns 12 and22), the above described method of electrical connection of the bentportions 16 and the flat portion 26 can be applied.

Between the semiconductor chip 30 and the substrate (for example, thefirst and second substrates 10 and 20) a resin (underfill) may beprovided. When an anisotropic conducting material is used, theanisotropic conducting material may also serve as a sealing resin.

In addition to face-down mounting, a face-up type of mounting using wirebonding, or the TAB mounting method using fingers (inner leads) may beapplied. On a single substrate (for example, the first and secondsubstrates 10 and 20), a plurality of semiconductor chips 30 may bemounted.

The semiconductor chips 30 mounted on the first and second substrates 10and 20 may be the same. Since the bent portions 16 and the flat portion26 are electrically connected, electrodes (pads) in the same positionson the two semiconductor chips 30 and one external terminal can beelectrically connected. Then if the semiconductor chip 30 is a memorydevice, from one external terminal information in each memory device inthe memory cell at the same address can be read out or written in. Itshould be noted that if each of the two semiconductor chips 30 has arespective chip select terminal, then by electrical connection todifferent external terminals, chip selection can be achieved. Electrodes(pads) in the same positions on the two semiconductor chips 30 may beelectrically connected to different external terminals 40. In this case,the first interconnect pattern 12 is formed so that the bent portions 16are not electrically connected to the semiconductor chip 30 mounted onthe first substrate 10. By inputting signals to different externalterminals 40, chip selection is achieved.

This embodiment of the semiconductor device has a plurality of externalterminals 40. The external terminals 40 are provided on at least eitherof (and possibly both) substrates positioned on the outside of aplurality of substrates, such as for example the first and secondsubstrates 10 and 20.

In this embodiment, the external terminals 40 are provided on the firstsubstrate 10. The external terminals 40 are electrically connected tothe first interconnect pattern 12. In more detail, through holes areformed in the first substrate 10, and with the through holes interposedthe external terminals 40 are provided on the first interconnect pattern12. The external terminals 40 are formed of solder or the like. Thethrough holes may be filled with solder, which is fused and formed intoballs by surface tension, or the solder balls may be mounted on aconducting material provided in the through holes. The inner surface ofthe through holes may be plated and the through holes formed. As amodification, the two sides of the first substrate 10 may beelectrically connected by through holes or the like, and on the surfaceof the first substrate 10 opposite to the first interconnect pattern 12,interconnects may be formed, and the external terminals provided onthese interconnects.

Alternatively, when the semiconductor device is mounted on amotherboard, solder cream spread on the motherboard may be used, and theexternal terminals may be formed on the first interconnect pattern 12(for example, on lands thereof) by the surface tension when this isfused. This semiconductor device is a so-called land grid array type ofsemiconductor device.

Alternatively, a part of the first substrate 10 may be extended beyondthe second substrate 20, and the external terminals may be formed onthis extended portion. In this case, a part of the first interconnectpattern 12 may be the external terminals. Alternatively, connectors tobe the external terminals may be mounted on the first substrate 10.

According to this embodiment, the bent portions 16 are formed by a partof the first interconnect pattern 12 projecting from the surface of thefirst substrate 10, and can have a simple construction. By means of thebent portions 16, electrical connection between the first and secondsubstrates 10 and 20 can be achieved, as a result of which it is notnecessary to form bumps.

This embodiment of the semiconductor device has the construction asdescribed above, and its method of manufacture is now described.

In this embodiment, a plurality of substrates (for example, the firstand second substrates 10 and 20 on which the first and secondinterconnect patterns 12 and 22 are formed) are taken. On at least onesubstrate (for example, the first and second substrates 10 and 20), thesemiconductor chip 30 is mounted. The first and second substrates 10 and20 are disposed so as to overlap, and the adjacent first and secondsubstrates 10 and 20 are electrically connected. It should be noted thatthe process of mounting the semiconductor chip 30 maybe carried outbefore the process of electrically connecting the first and secondsubstrates 10 and 20, or may be carried out thereafter, or may becarried out simultaneously therewith.

The electrical connection of the first and second substrates 10 and 20is, that is to say, the electrical connection of the first and secondinterconnect patterns 12 and 22 formed respectively thereon. The bentportions 16 formed on the first interconnect pattern 12 are electricallyconnected to the flat portions 26 on the second interconnect pattern 22.

The method of forming the bent portions 16 is now described withreference to FIG. 5. The bent portions 16 are formed by plasticdeformation of the first interconnect pattern 12. For example, the firstsubstrate 10 is positioned between a mold (for example, a metal die) 50having a projection 51 of a form which is the inverse of the depressedsurface of the bent portions 16 and a mold (for example, a metal die) 52having a depression 53 of a form which is the inverse of the projectedsurface of the bent portions 16. It should be noted that the projection51 is formed of a size to pass through the through holes 14. Next, bymeans of the molds 50 and 52, the first interconnect pattern 12 issubjected to press forming, and the bent portions 16 are formed.

The bent portions 16 may be formed at the stage of forming the firstsubstrate 10 (at a stage before the mounting process), or may be formedat the same time that the first and second interconnect patterns 12 and22 are connected. In this case, while forming the bent portions 16, thebent portions 16 and the flat portion 26 are finally bonded.

FIG. 6 illustrates a process of disposing a plurality of substrates soas to be overlaid. In this embodiment, since a plurality of substratesis disposed to be overlaid, substrate positioning is required. Here, theplurality of substrates (for example, the first and second substrates 10and 20) may be positioned by reference to the outer form.

For example, as shown in FIG. 6, container 70 is used in which adepression is formed. The depression formed in the container 70corresponds to the outer form of the first and second substrates 10 and20. In more detail, when the first and second substrates 10 and 20 areformed with the same outer form, and are disposed so as to be entirelyoverlaid, the inner side surface of the depression forms a verticalsurface. Therefore, when the first and second substrates 10 and 20 areinserted within the depression, they are mutually positioned withreference to their outer form. Then if the bent portions 16 and flatportion 26 are also formed to be accurately positioned with respect tothe outer form of the first and second substrates 10 and 20, they willbe accurately positioned. It should be noted that a part of the outerform of the first and second substrates 10 and 20 maybe used as areference for positioning. For example, the positioning may be carriedout with reference to the four corners of the first and secondsubstrates 10 and 20.

As a modification, as shown in FIG. 7, through holes 84 may be formed infirst and second substrates 80 and 90, and the positioning carried outwith the through holes 84 as reference. For example, through pins 86 maybe inserted in holes 84.

As shown in FIG. 6, for the bonding of the bent portions 16 and the flatportion 26, a tool 72 may be used. For example, at least one of pressureand heat is applied to the bent portions 16 by the tool 72. Theplurality of bent portions 16 and the plurality of flat portions 26maybe simultaneously bonded. When the interconnect pattern formed on atleast two substrates of three or more overlaid substrates has bentportions, then bonding of the flat portions of these may be carried outsimultaneously. In this way, the bent portions 16 and the flat portions26 are bonded.

To bond the bent portions 16 and the flat portions 26, the abovedescribed material (for example, an adhesive or the like) may beprovided in advance on at least one of the bent portions 16 and flatportions 26. When a thermosetting adhesive is used, by the applicationof heat the adhesive power of the adhesive is activated. If the step ofproviding the adhesive or the like in the bonding of the semiconductorchip 30, and the step of providing the adhesive or the like for bondingthe bent portions 16 and the flat portions 26 are carried outsimultaneously, the process can be simplified.

The bond between the bent portions 16 and the flat portions 26 may beany of (1) bonding with a brazing material including solder, (2) soliddiffusion bonding (metal bond) using the application of ultrasonicvibration and heat to clean surfaces, (3) bonding by mechanicalcrimping, and (4) adhesive conducting bonding by means of a conductingpaste or the like. Whichever method is used, the bent portions 16 andthe flat portions 26 may be bonded one at a time, or may be bonded morethan one at a time, or may all be bonded simultaneously. If the samemethod is used for the electrical connection of the semiconductor chip30 and the interconnect pattern, these preparatory steps are simplified.

According to this embodiment, the bent portions 16 are formed by bendinga part of the first interconnect pattern 16, and therefore can be formedsimply. Since the electrical connection between the first and secondsubstrates 10 and 20 is achieved by the bent portions 16, it is notnecessary to form bumps.

Second Embodiment

FIG. 8 shows a second embodiment of the semiconductor device to whichthe present invention is applied.

In this embodiment, the bent portions 116 project from the opposite sideof a first substrate 110 from that of the surface on which a firstinterconnect pattern 112 is formed. The bent portions 116 extend intothrough holes 114 formed in the first substrate 110.

The depression of the bent portions 116 may be filled with a resin 118.By means of the resin 118, the bent portions 116 are reinforced,excessive bending and deformation of the bent portions 116 by appliedstress is prevented, and the stress applied to the bent portions 116 canbe absorbed. By means of the resin 118, even if a split occurs in thebent portions 116, the destruction of the bent portions 116 can beprevented. Preferably the entire depression of the bent portions 116 isfilled with the resin 118.

The resin 118 deforms sufficiently to absorb stress, but preferably hascharacteristics such as to maintain a fixed form. The resin 118 ispreferably rich in softness, and rich in heat resistance. If a resinrich in softness is used, this is advantageous in the absorption ofexternally applied stress and thermal stress or the like by the resin.

As the resin 118 may be used, for example, a polyimide resin or thelike, and of these, one with a low Young's modulus (for example, anolefin polyimide resin, or as an example of other than a polyimide resinBCB made by Dow Chemical, or the like) is preferably used. Inparticular, it is preferable that the Young's modulus be at mostapproximately 300 kg/mm². As the resin 118, for example, a siliconedenatured polyimide resin, epoxy resin, silicone denatured epoxy resin,or the like may be used.

In this embodiment also, first and second substrates 110 and 120 aredisposed so as to be overlaid. The first interconnect pattern 112 ispositioned on the surface of the first substrate 110 opposite to that ofthe second substrate 120. A second interconnect pattern 122 ispositioned on the surface of the second substrate 120 on the side of thefirst substrate 110. The bent portions 116 projecting through thethrough holes 114 formed in the first substrate 110 are electricallyconnected to flat portions 126.

In this embodiment, a semiconductor chip 30 is mounted on each of thefirst and second substrates 110 and 120. On the first substrate 110, onthe opposite surface from the second substrate 120 is formed the firstinterconnect pattern 112, and on this surface the semiconductor chip 30is mounted. On the second substrate 120, the second interconnect pattern122 is formed on the side of the first substrate 110, and on thissurface the semiconductor chip 30 is mounted. That is to say, thesemiconductor chip 30 is disposed between the first and secondsubstrates 110 and 120.

The external terminals 40 are provided on the second substrate 120. Inmore detail, the same details of the external terminals 40 described inthe first embodiment can be applied to this embodiment.

In this embodiment, the description of the above first embodiment andits modifications can be applied. In this embodiment also, the effectdescribed in the first embodiment can be achieved.

Third Embodiment

FIG. 9 shows a third embodiment of the semiconductor device to which thepresent invention is applied. This embodiment differs from the secondembodiment in the following points.

On first and second substrates 130 and 140 are mounted semiconductorchips 150 and 152 of different sizes. External terminals 160 are formedby bending an interconnect pattern. For example, a second interconnectpattern 142 is bent to form external terminals 160. To the externalterminals 160, the description of the bent portions 16 described in thefirst embodiment can be applied.

In other respects, in this embodiment, the description described in thefirst embodiment and its modifications and the second embodiment can beapplied. In this embodiment also, the effect described in the firstembodiment can be achieved.

Fourth Embodiment

FIG. 10 shows a fourth embodiment of the semiconductor device to whichthe present invention is applied. This embodiment differs from the firstembodiment in the external terminals.

More specifically, in this embodiment, external terminals 180 areprovided on a second substrate 170. The external terminals 180 areformed by bending a second interconnect pattern 172. The description ofthe bent portions 16 described in the first embodiment can be applied tothe external terminals 180. In other respects, in FIG. 10, thesemiconductor device shown in FIG. 1 is shown upside down.

In other respects, in this embodiment, description of the firstembodiment and its modifications can be applied. In this embodimentalso, the effect described in the first embodiment can be achieved.

Fifth Embodiment

FIG. 11 shows a fifth embodiment of the semiconductor device to whichthe present invention is applied. This embodiment of the semiconductordevice differs from the semiconductor device described in the firstembodiment in that a semiconductor chip 30 is mounted one of the firstand second substrates 10 and 20 (in FIG. 11, the first substrate 10).

In this case, by means of the first interconnect pattern 12 formed onthe first substrate 10 (or as a modification the second interconnectpattern 22 formed on the second substrate 20), the same construction asthe multi-layer interconnect is obtained. By means of this, the use of amulti-layer substrate having an expensive jumper construction, or abuilt-up substrate is no longer required. The content of this embodimentcan also be applied to other embodiments. In this embodiment also, theeffect described in the first embodiment can be achieved.

Sixth Embodiment

FIG. 12 shows a sixth embodiment of the semiconductor device to whichthe present invention is applied.

In this embodiment, a first substrate 210 has a plurality of substrates202 and 204 disposed spaced apart and approximately in the same plane,and a first interconnect pattern 212. A part of the portion of the firstinterconnect pattern 212 which bridges the gap between the substrates202 and 204 (interconnect leads) is deformed so that bent portions 216are formed.

A second substrate 220 has a plurality of substrates 206 and 208disposed spaced apart and approximately in the same plane, and a secondinterconnect pattern 222. A part of the second interconnect pattern 222,for example at least a part of the portion bridging the gap between thesubstrates 206 and 208 (interconnect leads) is a flat portion 226. Thenthe bent portions 216 and flat portion 226 are bonded. According to thisembodiment, the interconnect leads connecting the substrates 202 and 204or substrates 206 and 208 can be used for electrical connection of thelaminated first and second substrates 210 and 220.

In other respects, in this embodiment, the description of the abovedescribed embodiments and their modifications can be applied. In thisembodiment also, the effect described in the first embodiment can beachieved.

Seventh Embodiment

FIG. 13 shows a seventh embodiment of the semiconductor device to whichthe present invention is applied.

In this embodiment, first and second substrates 230 and 240 formed of asoft material such as polyimide resin are disposed in a bent form. Partof a first interconnect pattern 232 passes through through holes 234formed in the first substrate 230, and bent portions 236 are formed. Thebent portions 236 are bonded to a portion (flat portion 246) exposedthrough through holes 244 in a second interconnect pattern 242.

In other respects, in this embodiment, the description of the abovedescribed embodiments and their modifications can be applied. In thisembodiment also, the effect described in the first embodiment can beachieved.

Eighth Embodiment

FIG. 14 shows an eighth embodiment of the semiconductor device to whichthe present invention is applied. This embodiment of the semiconductordevice has three substrates 250, 260, and 270, but may have more thanthree substrates. In the event that there are more than threesubstrates, the term “three substrates” may refer to any threesubstrates of the more than three substrates, but may be threeconsecutively adjacent substrates.

Of the three substrates 250, 260, and 270, the central substrate 260 isa first substrate, and bent portions 266 are formed projecting from eachof both sides. The description of the first substrate and bent portionsin the above described embodiments and their modifications applies tothe substrate 260 and bent portions 266.

Of the three substrates 250, 260, and 270 the outer substrates 250 and270 are second substrates, and flat portions 256 and 276 are formed. Thedescription of the second substrate and flat portion in the abovedescribed embodiments and their modifications applies to the substrates250 and 270 and flat portions 256 and 276.

In other respects, in this embodiment, the description of the abovedescribed embodiments and their modifications can be applied. In thisembodiment also, the effect described in the first embodiment can beachieved.

It should be noted that in the method of manufacture of this embodimentof the semiconductor device, all of the bent portions 266 and all of theflat portions 256 and 276 may be simultaneously bonded after overlayingthe three or more substrates 250, 260, and 270. By doing this, theprocess can be made shorter.

Ninth Embodiment

FIG. 15 shows a ninth embodiment of the semiconductor device to whichthe present invention is applied. This embodiment of the semiconductordevice has three substrates 310, 320, and 330, but may have more thanthree substrates. In the event that there are more than threesubstrates, the term “three substrates” may refer to any threesubstrates of the more than three substrates, but may be threeconsecutively adjacent substrates.

Of the three substrate s 310, 320, and 330, the outer substrates 310 and330 are first substrates, and bent portions 316 and 336 are formed. Thedescription of the first substrate and bent portions in the abovedescribed embodiments and their modifications applies to the substrates310 and 330 and bent portions 316 and 336.

Of the three substrates 310, 320, and 330, the central substrate 320 isa second substrate, and a plurality of flat portions 326 is formed. Torespective flat portions 326, bent portions 316 and 336 are bonded. Thedescription of the second substrate and flat portion in the abovedescribed embodiments and their modifications applies to the substrate320 and flat portions 326.

In other respects, in this embodiment, the description of the abovedescribed embodiments and their modifications can be applied. In thisembodiment also, the effect described in the first embodiment can beachieved.

It should be noted that in the method of manufacture of this embodimentof the semiconductor device, all of the bent portions 316 and 336 andall of the flat portions 326 may be simultaneously bonded afteroverlaying all of the three or more substrates 310, 320, and 330.

By means of this, the bent portions 316 and 336 formed on the two ormore substrates 310 and 330, and the flat portions 326 can be bonded ina single operation, and the process can be made shorter.

Tenth Embodiment

FIG. 16 shows a tenth embodiment of the semiconductor device to whichthe present invention is applied. This embodiment of the semiconductordevice has three substrates 340, 350, and 360, but may have more thanthree substrates.

One of the two substrates 340 and 360 positioned on the outside (in theexample in FIG. 16, the substrate 360) is a first substrate, and bentportions 366 are formed. The other of the two substrates 340 and 360positioned on the outside (in the example in FIG. 16, the substrate 340)is a second substrate, and a flat portion 346 is formed.

The at least one substrate positioned on the inside (in the example ofFIG. 16, the substrate 350) has bent portions 356 and flat portion 357.The substrate 350 is a first substrate with respect to one of theadjacent substrates 340 and 360 (in the example of FIG. 16, thesubstrate 340). The substrate 350 is a second substrate with respect tothe other of the adjacent substrates 340 and 360 (in the example of FIG.16, the substrate 360). By means of this, the substrate 350 isconstructed to function as both a first substrate and a secondsubstrate.

It should be noted that the description of the first and secondsubstrates, the bent portions and the flat portion in the abovedescribed embodiments and their modifications applies to the substrates340, 350, and 360, the bent portions 356 and 366, and the flat portions346 and 357.

In other respects, in this embodiment, the description of the abovedescribed embodiments and their modifications can be applied. In thisembodiment also, the effect described in the first embodiment can beachieved.

It should be noted that in the method of manufacture of this embodimentof the semiconductor device, all of the bent portions 356 and 366 andall of the flat portions 346 and 357 may be simultaneously bonded afteroverlaying all of the three or more substrates 340, 350, and 360.

By means of this, the bent portions 356 and 366 and the flat portions346 and 357 formed on the two or more substrate 350 and 360 can bebonded in a single operation, and the process can be made shorter.

Other Embodiments

FIG. 17 shows a circuit board 1000 on which is mounted a semiconductordevice 1 manufactured by the method to which the above describedembodiments relate. For the circuit board 1000 is generally used anorganic substrate such as a glass epoxy substrate or the like. On thecircuit board 1000, an interconnect pattern of for example copper isformed to constitute a desired circuit. Then, by mechanical connectionof the interconnect pattern and the external terminals of thesemiconductor device 1, electrical conduction is achieved. Then as anelectronic instrument equipped with the semiconductor device 1 andcircuit board 1000, in FIG. 18 is shown a notebook personal computer2000, and in FIG. 19 is shown a mobile telephone 3000.

It should be noted that in place of the semiconductor chip used in thisembodiment, an electronic element (whether an active element or apassive element) can be mounted on a first or second substrate tomanufacture an electronic component. As electronic componentsmanufactured using such an electronic element maybe cited, for example,optical elements, resistors, capacitors, coils, oscillators, filters,temperature sensors, thermistors, varistors, variable resistors, andfuses.

Furthermore, in addition to a semiconductor chip, the above describedelectronic element may be mounted in combination on a first or secondsubstrate, to constitute a mounting module.

What is claimed is:
 1. A semiconductor device comprising: a plurality of substrates which have interconnect patterns and are disposed so as to be overlaid; and a semiconductor chip mounted on at least one of the substrates; wherein a first interconnect pattern formed on a first substrate which is one of two substrates included in the plurality of overlaid substrates has at least one bent portion which projects from a surface of the first substrate; and wherein the bent portion is electrically connected to at least one flat portion of a second interconnect pattern formed on a second substrate of the two substrates.
 2. The semiconductor device as defined in claim 1, wherein a through hole is formed in the first substrate; and wherein the bent portion enters the through hole, and projects from a surface of the first substrate opposite to the surface on which the first interconnect pattern is formed.
 3. The semiconductor device as defined in claim 1, wherein a through hole is formed in the first substrate; and wherein the bent portion is positioned over the through hole and projects from the surface of the first substrate on which the first interconnect pattern is formed.
 4. The semiconductor device as defined in claim 2, wherein a plurality of the bent portions are formed within the through hole.
 5. The semiconductor device as defined in claim 3, wherein a plurality of the bent portions are formed over the through hole.
 6. The semiconductor device as defined in claim 2, wherein a plurality of the through holes are formed in the first substrate; wherein a plurality of the bent portions are formed in the first interconnect pattern; and wherein each of the bent portions is formed so as to be positioned over one of the through holes.
 7. The semiconductor device as defined in claim 3, wherein a plurality of the through holes are formed in the first substrate; wherein a plurality of the bent portions are formed in the first interconnect pattern; and wherein each of the bent portions is formed so as to be positioned over one of the through holes.
 8. The semiconductor device as defined in claim 1, wherein the second interconnect pattern is formed on a surface of the second substrate on the side of the first substrate.
 9. The semiconductor device as defined in claim 1, wherein the second interconnect pattern is formed on a surface of the second substrate opposite to the surface of the second substrate which faces to the first substrate; and wherein the bent position is electrically connected to the second interconnect pattern through the through hole formed in the second substrate.
 10. The semiconductor device as defined in claim 1, wherein the semiconductor chip is provided between the first and second substrates; and wherein the bent portion projects to the side of the semiconductor chip, and is formed to be higher than the semiconductor chip.
 11. The semiconductor device as defined in claim 1, wherein the semiconductor chip is provided on each of the first and second substrates.
 12. The semiconductor device as defined in claim 1, wherein the semiconductor chip is provided on one of the first and second substrates.
 13. The semiconductor device as defined in claim 1, wherein the number of the substrates provided to be overlaid is three or more; wherein a central substrate of the three substrates is the first substrate, and the bent portions project from both surfaces of the first substrate; and wherein outer substrates of the three substrates are the second substrate.
 14. The semiconductor device as defined in claim 1, wherein the number of the substrates provided to be overlaid is three or more; and wherein a central substrate of the three substrates is the second substrate, and outer substrates are the first substrate.
 15. The semiconductor device as defined in claim 1, wherein the number of the substrates provided to be overlaid is three or more; wherein one of two outer substrates of the overlaid substrates is the first substrate, and the other is the second substrate; and wherein at least one center substrate of the overlaid substrates has the bent portion and the flat portion, and is the first substrate with respect to one of the two outer substrates, and is the second substrate with respect to the other of the two outer substrates.
 16. A circuit board on which is mounted the semiconductor device as defined in claim
 1. 17. An electronic instrument having the semiconductor device as defined in claim
 1. 18. A method of manufacture of a semiconductor device, comprising the steps of: mounting a semiconductor chip on at least one of a plurality of substrates having interconnect patterns; providing the substrates so as to be overlaid; and electrically connecting two substrates of the overlaid substrates; wherein a first interconnect pattern formed on a first substrate of the two substrates has a bent portion which projects from a surface of the first substrate; and wherein the bent portion is electrically connected to a flat portion of a second interconnect pattern formed on a second substrate of the two substrates.
 19. The method of manufacture of a semiconductor device as defined in claim 18, wherein the plurality of substrates are positioned with the outer form of the substrates as a reference.
 20. The method of manufacture of a semiconductor device as defined in claim 18, wherein the plurality of substrates are positioned with holes formed in the substrates as a reference.
 21. The method of manufacture of a semiconductor device as defined in claim 18, wherein at least one of pressure and heat is applied to the bent portion to electrically connect the bent portion to the flat portion.
 22. The method of manufacture of a semiconductor device as defined in claim 21, wherein the bent portion is formed on each of the interconnect patterns formed on the substrates; and wherein the bent portion formed on each of the substrates is electrically connected to the flat portion in a single operation. 